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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT240 Octal buffer/line driver; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting FEATURES * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION 74HC/HCT240 The 74HC/HCT240 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT240 are octal inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The "240" is identical to the "244" but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay 1An to 1Yn; 2An to 2Yn input capacitance power dissipation capacitance per buffer notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 9 9 HCT ns UNIT CI CPD Notes 3.5 30 3.5 30 pF pF 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". December 1990 2 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting PIN DESCRIPTION PIN NO. 1 2, 4, 6, 8 3, 5, 7, 9 10 17, 15, 13, 11 18, 16, 14, 12 19 20 SYMBOL 1OE 1A0 to 1A3 2Y0 to 2Y3 GND 2A0 to 2A3 1Y0 to 1Y3 2OE VCC NAME AND FUNCTION output enable input (active LOW) data inputs bus outputs ground (0 V) data inputs bus outputs output enable input (active LOW) positive supply voltage 74HC/HCT240 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting FUNCTION TABLE INPUTS nOE L L H Notes L H X nAn 74HC/HCT240 OUTPUT nYn H L Z 1. H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state Fig.4 Functional diagram. December 1990 4 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER 74HC/HCT240 TEST CONDITIONS VCC WAVEFORMS (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.5 +25 min. typ. -40 to +85 max. min. -40 to +125 min. max. max. 125 25 21 190 38 33 190 38 33 75 15 13 tPHL/ tPLH propagation delay 1An to 1Yn; 2An to 2Yn tPZH/ tPZL 3-state output enable time 1OE to 1Yn; 2OE to 2Yn tPHZ/ tPLZ 3-state output disable time 1OE to 1Yn; 2OE to 2Yn tTHL/ tTLH output transition time 30 11 9 39 14 11 41 15 12 14 5 4 100 20 17 150 30 26 150 30 26 60 12 10 150 30 26 225 45 38 225 45 38 90 18 15 ns Fig.6 ns Fig.6 ns Fig.5 December 1990 5 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver IICC category: MSI Note to HCT types 74HC/HCT240 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT 1An 2An 1OE 2OE UNIT LOAD COEFFICIENT 1.50 1.50 0.70 0.70 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 30 ns 4.5 Fig.5 UNIT V WAVEFORMS CC (V) TEST CONDITIONS min. typ. max. min. max. min. tPHL/ tPLH propagation delay 1An to 1Yn; 2An to 2Yn 3-state output enable time 1OE to 1Yn; 2OE to 2Yn 3-state output disable time 1OE to 1Yn; 2OE to 2Yn output transition time 11 20 25 tPZH/ tPZL 13 30 38 45 ns 4.5 Fig.6 tPHZ/ tPLZ 13 25 31 38 ns 4.5 Fig.6 tTHL/ tTLH 5 12 15 18 ns 4.5 Fig.5 December 1990 6 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting AC WAVEFORMS 74HC/HCT240 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.5 Waveforms showing the input (1An, 2An) to output (1Yn, 2Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7 |
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